1. Field
Exemplary embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with a vertical gate transistor.
2. Description of the Related Art
In a semiconductor device, to achieve a high density and a short channel margin, transistors with a three-dimensional structure may be implemented. Among these transistors, a vertical gate transistor with a vertical channel has been used in the semiconductor device.
In a vertical gate transistor, since a channel is formed in a vertical direction with respect to a substrate, a gate dielectric layer and gate electrodes are also formed in the vertical direction. To separate the gate electrodes, dry etching is performed using spacers. The gate electrodes are referred to as vertical gates.
FIGS. 1A and 1B are views illustrating a conventional method for manufacturing a vertical gate transistor.
Referring to FIG. 1A, a plurality of pillars 12 are formed by etching a semiconductor substrate 11. A hard mask layer 13 is used as an etch barrier to form the pillars 12. The pillars 12 become vertical channels.
A gate dielectric layer 14 is formed on the surfaces of the pillars 12. Subsequently, a conductive layer 15, which is to be used as gate electrodes, is formed on the entire surface including the gate dielectric layer 14. The conductive layer 15 is formed to gap-fill the spaces between the pillars 12. Subsequently, planarization and etch-back processes are performed.
A dielectric layer to be used as spacers 16 is formed on the conductive layer 15. After performing spacer etching, the conductive layer 15 is etched using the spacers 16 as an etch barrier. As a result, vertical gates are formed. When etching the conductive layer 15, dry etching, for example, plasma etching, is used.
FIG. 1B illustrates the semiconductor device after etching of the conductive layer 15 is completed and vertical gates 15A are formed.
However, in the conventional art, electron shadowing 17 occurs at the top of a narrow trench between the pillars 12 by an ion sheath under a plasma atmosphere. As a result, electrons may not reach the bottom of the trench. Positive ions 18 move to the bottom of the trench due to an attractive force. Therefore, damage may occur at the gate dielectric layer 14 as a result of the collection of positive ions 18 at the bottom of the gap. More specifically, a plasma-induced damage (PID) occurs due to a structural aspect. In particular, since the thickness of the gate dielectric layer 14 is thinnest on an edge 19 of the lower end of each pillar 12, degradation due to the plasma-induced damage may become serious at the edge 19.